Recently, by using a ferroelectric material in the capacitor of memory cell, a ferroelectric memory device realizing nonvolatility of stored data is devised. The ferroelectric capacitor has a hysteresis characteristic, and if the electric field is zero, a residual polarization of different polarity depending on the hysteresis is left over. By expressing the stored data by the residual polarization of the ferroelectric capacitor, a nonvolatile memory device is realized.
The specification of U.S. Pat. No. 4,873,664 discloses two types of ferroelectric memory device. In a first type, a memory cell is composed of one transistor and one capacitor per bit (1T1C), and a reference memory cell is provided in, for example, every 256 main body memory cells (normal cells). In a second type, without using reference memory cell, a memory cell is composed of two transistors and two capacitors per bit (2T2C), in which a pair of complementary data are stored in a pair of ferroelectric capacitors.
As the ferroelectric material for composing capacitor, KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3 are known among others. According to PCT International Disclosure No. WO93/12542 Publication, ferroelectric materials extremely small in fatigue as compared with PbTiO.sub.3 --PbZrO.sub.3 suited to ferroelectric memory device are also known.
For example, the constitution of ferroelectric memory device in 2T2C composition and its conventional operation mode are briefly described below. FIG. 31 is a memory cell block diagram, FIG. 32 is a sense amplifier circuit diagram, FIG. 33 is an operation timing chart, FIG. 34 is an operation hysteresis characteristic diagram of ferroelectric capacitor, and FIG. 35 is a relation diagram of supply voltage and bit line voltage when reading out data.
In FIG. 31, C00 to C37 refer to ferroelectric capacitors, CPD is a cell plate driver, SA0 to SA3 are sense amplifiers, CP is a cell plate signal, WL0 to WL3 are word lines, and BL0 to BL3, /BL0 to /BL3 are bit lines. In FIG. 32, BP is a bit line precharge signal, /SAP, SAN are sense amplifier control signals, VSS is a grounding voltage, and VDD is a supply voltage.
In FIG. 34, points A to F refer to hysteresis characteristics when positive and negative electric fields are applied to both electrodes of the ferroelectric capacitor, and points P901 to P903 indicate the reading state of the ferroelectric capacitor.
In the memory cell composition, for example, bit lines BL0 and /BL0 are connected to the sense amplifier SA0, and ferroelectric capacitors C00, C01 are connected to the bit lines BL0 and /BL0 through an N-channel MOS transistor having word line WL0 as its gate. The ferroelectric capacitors C00, C01 are connected to the cell plate signal CP which is driven by the cell plate driver CPD. The sense amplifier SA0 is driven by sense amplifier control signals /SAP, SAN, and the circuit is thus composed so that precharge of bit lines BL0 and /BL0 is controlled by the bit line precharge signal BP.
The operation is further described by referring to FIG. 33 and FIG. 34.
First, the bit lines BL0 and /BL0 are precharged to logic voltage L by the bit line precharge signal BP. Then the bit line precharge signal BP is set to logic voltage L, and the bit lines BL0 and /BL0 come into floating state.
The initial states of the ferroelectric capacitors C00 and C01 are as indicated by point B and point E in FIG. 34, respectively. Consequently, the word line WL0 is set to logic voltage H, and the cell plate signal CP to logic voltage H. Herein, the potential level of the logic voltage H of the word line WL0 is a voltage boosted above the supply voltage VDD. At this time, an electric field is applied to both. electrodes of the ferroelectric capacitors C00 and C01, and potentials determined by the capacity ratio of the capacity of the ferroelectric capacitor and the bit line capacity including the parasitic capacity are produced in the bit lines BL0 and /BL0. The both voltages are read out to be data. The states of the ferroelectric capacitors C00 and C01 are as indicated by point P901 and point P902 in FIG. 34.
Afterwards, by setting the sense amplifier control signal /SAP to logic voltage L and SAN to logic voltage H, the sense amplifier SA0 is put in operation. As a result, the potentials being read out from the bit lines are amplified to the supply voltage VDD and grounding voltage VSS. That is, by the operation of the sense amplifier SA0, the supply voltage VDD is applied to the bit line BL0 showing the higher potential, of the potentials being read out from the bit Lines BL0 and /BL0. As a result, the potential of the bit line BL0 is changed to logic voltage H. At the same time, the grounding voltage VSS is applied to the bit line /BL0 showing the lower potential, and the potential of the bit line /BL0 is changed to logic voltage L. In this way, the potentials of the both bit lines can be varied to the logic voltage H and L, depending on the difference in their potential. That is, the potential difference of the two bit lines is amplified to the potential difference of the supply voltage VDD and grounding voltage VSS by the sense amplifier SA0. Such operation is only mentioned in this specification that the potentials being read out from the bit lines are amplified to the supply voltage VDD and grounding voltage VSS.
At this time, the states of the ferroelectric capacitors C00 and C01 are respectively point P903 and point D in FIG. 34.
Next, as the rewriting operation, consequently, the cell plate signal CP is set to logic voltage L. This rewriting operation is intended to prevent decrease of polarization level of ferroelectric capacitor, so that the next reading operation may be done smoothly. The states of the ferroelectric capacitors C00 and C01 are respectively point A and point E in FIG. 34.
Later, stopping the sense amplifier, the bit lines BL0 and /BL0 are precharged to logic voltage L by the bit line precharge signal BP. The states of the ferroelectric capacitors C00 and C01 are respectively point B and point E in FIG. 34.
As this reading operation, setting the cell plate signal CP to logic voltage H, the relation between the potentials of the bit lines BL0 and /BL0 and the supply voltage when data is read out into the bit lines BL0 and /BL0 is shown in FIG. 35. The broken line shown in FIG. 35 refers to the potential of the bit line BL0 when the potential level of the logic voltage H of the word line WL0 is sufficiently higher than the supply voltage VDD and there is no effect of threshold value of the memory cell transistor. Actually, as indicated by solid line, the potential is lower than the dotted line potential.
In the conventional ferroelectric memory device of 2T2C composition, however, the potential being read out into the bit line may be lowered by the effects of threshold value of the memory cell transistor as described above, and in this case, therefore, the potential difference between a pair of bit lines, that is, the potential difference between the bit lines BL0 and /BL0 becomes small. In particular, the effect is significant at low voltage, and the low voltage operation may be difficult.
To solve this problem, if the word line is boosted, the circuit is complicated, also boosting of the word line by high supply voltage brings about another problems in the withstand voltage of the memory cell transistor and others.
As the bit line logic voltage L side operation in the reading operation, for the ferroelectric capacitor, a same voltage as the supply voltage is applied in one direction, it is disadvantageous for the life of the number of times of reading of the ferroelectric capacitor. These problems are not limited to the ferroelectric memory device of 2T2C composition alone, but are commonly seen also in the ferro,electric memory device of 1T1C composition.